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Efficient Improvement of Hot-Carrier-Induced Devices Degradation for Sub-0.1 μm Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor Technology

Identifieur interne : 00A652 ( Main/Repository ); précédent : 00A651; suivant : 00A653

Efficient Improvement of Hot-Carrier-Induced Devices Degradation for Sub-0.1 μm Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor Technology

Auteurs : RBID : Pascal:04-0285575

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Abstract

The effect of post-thermal annealing (PA) after In-halo and As-halo implantation on the reliability of sub-0.1 μm complementary metal-oxide-semiconductor field-effect-transistors was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving hot-carrier-induced devices degradation. The optimal results of device performance as well as of reliability can be obtained with post-annealing treatment performed at medium temperatures (e.g., 900°C) for a longer time. © 2004 The Japan Society of Applied Physics

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